Name: On-Chip Training Npu - Algorithm, Architecture and Soc Design
Price: 317.42 NZD
Availability: InStock
Author: Han, Donghyeon ; Yoo, Hoi-Jun
ISBN: 9783031342363

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On-Chip Training Npu - Algorithm, Architecture and Soc Design

Type

Physical Book

Author

Hoi-Jun Yoo

Donghyeon Han

Publisher

Springer

Language

English

Pages

237

Format

Hardcover

Dimensions

23.4 x 15.6 x 1.6 cm

Weight

0.54 kg.

ISBN13

9783031342363

Synopsis "On-Chip Training Npu - Algorithm, Architecture and Soc Design"

Unlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and history surrounding the development of on-device DNN training, as well as on-device training semiconductors and SoC design examples to facilitate understanding.

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On-Chip Training Npu - Algorithm, Architecture and Soc Design - Han, Donghyeon ; Yoo, Hoi-Jun

Synopsis "On-Chip Training Npu - Algorithm, Architecture and Soc Design"

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